Distributed Simulation of Asynchronous Computer Architectures: the Program Driven Approach

ARCHITECTURES: THE PROGRAM DRIVEN APPROACH G. Theodoropoulos, J. V. Woods Department of Computer Science University of Manchester Oxford Road, Manchester M13 9PL, U.K. ABSTRACT Recently, there has been a resurgence of interest in asynchronous design techniques due to the potential of asynchronous logic for higher performance and lower power consumption. The research activity in this area has pointed to the need for suitable techniques for modeling and simulating asynchronous systems. Occam 1 allows the rapid development of distributed simulation models of asynchronous systems but its distributed nature introduces timing modeling problems. This paper presents an approach for dealing with these problems. INTRODUCTION Conventional synchronous architectures use design techniques based on global clocking whereby all the functional units operate in lockstep under the control of a central clock. As VLSI technology advances and systems become larger, faster and more complex, timing problems become increasingly severe and account for more and more of the design and debugging expense. Increased clock speeds make on-chip clock skew signi cant and interchip skew a major problem. One solution to clock-related timing problems is to use asynchronous design techniques without any global synchronization signals to control the rate at which different elements operate (Seitz 1980). Another potential advantage of asynchronous logic, which recently has led to a resurgence of interest in its use, is lower power consumption. An asynchronous system may be designed as a set of functional modules each operating at its own rate and cooperating through communication. The communication protocol synchronizes the modules involved in the communication and allows data to be shared between them. There exist many different approaches for designing asynchronous systems (Gopal. 1990). Sutherland's \Micropipelines" (Suther. 1989) use bundled data with an event-signaled handshake protocol for synchronization ( gures 1,2). Following Sutherland's approach, the AMULET group at the University of Manchester have designed and implemented AMULET1, an asynchronous version of the ARM processor (Furber 1993). The recent research activity in the area of asynchronous systems has pointed to the need for suitable techniques for modeling and simulating them (Udding 1991). Several notations and techniques have been suggested for this purpose (Hauck 1993). CSP in particular has attracted the interest of many researchers due to the 1occam is a registered trademark of INMOS Group of Companies. Figure 1: The bundled data interface of micropipelines Figure 2: Event processing blocks strong relationship between its semantics and nondeterministic, concurrent behaviour of asynchronous systems (Martin 1986, Brunv. 1989). To support the design of AMULET1, a methodology for using occam, a CSP based parallel language that supports synchronous, unbu ered interprocess communication, for building Register Transfer Level executable models of asynchronous architectures has been developed (Theodor. 1994a) Using this methodology, an asynchronous architecture is modeled as a set of concurrent communicating occam processes. The processes are entirely data-driven, and self scheduled. Two channels are used for the synchronization of communicating processes, one for Request/data and one for the Acknowledge signal. To describe the nondeterministic behaviour of arbiters, the occam ALT statement is used. TIMING